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S72WS-N Based MCP/PoP Products
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus
256/512 Mb Simultaneous Read/Write, Burst Mode Flash Memory 512 Mb NAND Flash 1024 Mb NAND Interface ORNAND Flash Memory on Bus 1 512/256/128 Mb (8M/4M/2M x 16-bit x 4 Banks) Mobile SDRAM on Bus 2
Data Sheet
ADVANCE INFORMATION
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See "Notice On Data Sheet Designations" for definitions.
Publication Number S72WS-N_00
Revision A
Amendment 8
Issue Date June 1, 2006
Advance
Information
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
S72WS-N based MCP/PoP Products
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus
256/512 Mb Simultaneous Read/Write, Burst Mode Flash Memory 512 Mb NAND Flash 1024 Mb NAND Interface ORNAND Flash Memory on Bus 1 512/256/128 Mb (8M/4M/2M x 16-bit x 4 Banks) Mobile SDRAM on Bus 2
Data Sheet
ADVANCE INFORMATION
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
High Performance
Flash access time: 80 ns for NOR Flash, 25 ns for ORNAND Flash Flash burst frequencies: 54 MHz, 66MHz, 80MHz Mobile SDRAM burst frequency: 104 MHz, 133 MHz (DDR) Package: -- 9.0 x 12.0 mm MCP BGA -- 11.0 x 13.0 mm MCP BGA -- 15.0 x 15.0 x 1.2 mm MCP Package-on-Package (PoP) Operating Temperature -- -25C to +85C (wireless)
General Description
The S72WS series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One or two NOR flash memory dies One NAND Interface ORNAND die Separate bus for one or more Mobile SDRAM die The products covered by this document are listed in the table below.
Device S72WS256ND0 S72WS256NDE S72WS256NEE S72WS512NFG S72WS512NEG S72WS512NEF S72WS512NFF X X X X X X X X X X X X X X X NOR Flash Density 512Mb 256Mb X 128Mb NAND Flash Density 1024Mb 512Mb SDRAM Density 512Mb 256Mb 128Mb X X
Note: For a list of PoP OPNs, please contact the local sales representative or refer to the Ordering Information valid combinations tables.
For detailed specifications, please refer to the individual data sheets.
Document S29WS256N S30MS01GP/512P 128 Mb Mobile SDRAM Type 1 128 Mb Mobile SDRAM Type 2 128 Mb Mobile DDR-DRAM Type 5 256 Mb Mobile SDRAM Type 2 512 Mb Mobile DDR-DRAM Type 1 512 Mb Mobile SDRAM Type 4 512 Mb NAND Type 1 512 Mb Mobile DDR-DRAM Type 5 512 Mb Mobile DDR-DRAM Type 2 Publication Identification Number (PID) S29WS-N_00 S30MS-P_00 SDRAM_01 SDRAM_05 SDRAM_07 SDRAM_05 SDRAM_09 SDRAM_06 NAND_01 DRAM_04 DRAM_05
Publication Number S72WS-N_00
Revision A
Amendment 8
Issue Date June 1, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice
Advance
Information
Table of Contents
S72WS-N Based MCP/PoP Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
1 2 3 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 NOR Flash + DRAM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 NOR Flash + ORNAND Flash + DRAM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 NOR Flash + ORNAND Flash + DRAM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 2 x 256Mb NOR Flash with 256Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 2 x 256Mb NOR Flash with 128Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 256Mb NOR Flash with 128Mb SDR/DDR-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 512 Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256-Mb SDRAM on Bus 2 . . . . . . . . . . . . . . . 9 3.4.1 x16 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 512Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256 Mb SDRAM on Bus 2 . . . . . . . . . . . . . . . .10 3.5.1 x8 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.6 512Mb NOR Flash with 512-Mb NAND on Bus 1 and 512-Mb SDRAM on Bus 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6.1 x16 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6.2 Connection Diagram for 15 x 15 Package-on-Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 Lookahead Diagram on Split Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.8 NOR Flash and DRAM Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.8.1 ORNAND Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 TLD137--137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 FEA137--137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 FVD137--137-ball Fine-Pitch Ball Grid Array (FBGA) 11 x 13 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 BWA160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5 BWB160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6 BTA160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.7 ALH160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MCP Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 5
6
2
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
Advance
Information
1
1.1
Product Selector Guide
NOR Flash + DRAM Products
Device-Model# S72WS256ND0BAWB7 S72WS256ND0BAWBB S72WS256NDEBAWU7 S72WS256NDEBAWUB S72WS256NEEBAWU7 S72WS256NEEBAWUB S72WS256ND0BFWB7 S72WS256ND0BFWBB S72WS256NDEBFWU7 S72WS256NDEBFWUB S72WS256NEEBFWU7 S72WS256NEEBFWUB S72WS256ND0KFWD3 256 Mb S72WS256ND0BFW93 66 MHz 128 256 Mb 256 Mb 54 MHz 256 133 MHz (DDR) 133 MHz (DDR) 256 Mb -- 54 MHz 256 Mb 256 Mb 54 MHz 256 128 128 104 MHz 104 MHz Flash Density (Code) 256 Mb Flash Density (Data) -- Burst Speed (MHz) 54 MHz SDRAM Density 128 128 104 MHz SDRAM burst Speed (MHz) 104 MHz DRAM Supplier 1 2 1 2 1 2 1 2 1 2 1 2 5 sector unprotected sector unprotected 15x15x1.25 9x12x1.2 sector unprotected 9x12x1.4 sector unprotected 9x12x1.2 sector unprotected 9x12x1.4 DYB sector unprotected Package 9x12x1.2
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
3
Advance
Information
1.2
NOR Flash + ORNAND Flash + DRAM Products
Device-Model# S72WS512NFFBFWZ2 S72WS512NFFBFWZJ S72WS512NFG-L7 S72WS512NFG-L6 S72WS512NFG-L5 S72WS512NFG-47 S72WS512NFG-46 S72WS512NFG-45 S72WS512NFG-LZ S72WS512NFG-LY S72WS512NFG-LW S72WS512NFG-4Z S72WS512NFG-4Y S72WS512NFG-4W S72WS512NFG-N7 S72WS512NFG-N6 S72WS512NFG-N5 S72WS512NFG-67 S72WS512NFG-66 S72WS512NFG-65 S72WS512NFG-NZ S72WS512NFG-NY S72WS512NFG-NW S72WS512NFG-6Z S72WS512NFG-6Y S72WS512NFG-6W S72WS512NEG-LZ S72WS512NEG-LY S72WS512NEG-LW S72WS512NEG-4Z S72WS512NEG-4Y S72WS512NEG-4W S72WS512NEG-NZ S72WS512NEG-NY S72WS512NEG-NW S72WS512NEG-6Z S72WS512NEG-6Y S72WS512NEG-6W S72WS512NEFKFWHJ S72WS512NFFKFWZ2 S72WS512NFFKFWZJ 512Mb 512Mb (NAND) 256Mb 66MHz 512Mb 133MHz (DDR) 256 Mb 512Mb 1024Mb 512Mb NOR ORNAND SDRAM Flash Flash Density Density Density 512Mb (NAND) Flash Speed DRAM Speed 133MHz (DDR) Supplier DRAM Type 1 DRAM Type 5 X16 ORNAND Bus Width ECC required? Package
66MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz 54MHz 66MHz 80MHz
Yes
11x13x1.4mm
DRAM Type 4 X8 No X16 DRAM Type 2 X8
X16 DRAM Type 4 X8 104MHz X16 Yes 11x13x1.4mm
X8
X16 DRAM Type 2 X8 No
X16 Yes X8 DRAM Type2 DRAM Type 1 DRAM Type 5 x16 Yes
15x15x1.25mm 15x15x1.25mm 15x15x1.25mm
4
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
Advance
Information
2
2.1
MCP Block Diagram
NOR Flash + ORNAND Flash + DRAM Products
F-AVD# F-CLK F-ACC F-WP# F-RESET# F1-CE# F-WE# F-OE# F-A23:A0 F-VCCQ F2-CE# AVD# CLK ACC WP# RESET# CE# WE# WS256N OE# A23-A0 Vss CE# N-Vcc N-WP# N-CE# N-WE# N-RE# N-ALE N-CLE N-PRE WP# CE# WE# RE# ALE RY/BY# CLE PRE Vss RY/BY# MS01GP IO0:7 DQ0:7 DQ0:7 RDY DQ8:15 RDY DQ8:15 F-Vcc
D-Vcc D-A12-A0 D-CE# D-WE# D-BA0 D-BA1 D-CKE D-RAS# D-CAS# D-DM0 D-DM1 A12-A0 CE# WE# BA0 BA1 CKE RAS# CAS# DM0 DM1 D-Vss
V-Vccq DQ0:15 D-DQ15-DQ0
SDRAM
D-Vssq
Notes: 1. For a one-Flash configuration, F1-CE# = CE#. For a two-Flash configuration, F1-CE# = CE for Flash 1 and F2-CE# = CE for Flash 2; F2-CE# is the chip-enable pin for the second Flash.
2. If ORNAND is not present in the MCP, then the MS01GP block will not be present in the figure above. In that case, the common signals go only to the WS256N flash, while the SDRAM signals remain unchanged. 3. If ORNAND supports a x16 bus, then NOR DQ0-DQ15 is shared with ORNAND I/O0-I/O15.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
5
Advance
Information
3
3.1
Connection Diagram
2 x 256Mb NOR Flash with 256Mb SDRAM
137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1
D-CKE
A2 D-CLK
A3
RFU
A4
RFU
A5
D-VSS
A6
D-VCC
A7
D-A12
A8
D-A11
A9
D-VSS
A10
D-CE#
B1
B2
B3
D-A9
B4
D-A8
B5
B6
B7
D-A7
B8
D-A6
B9
RFU
B10
D-CAS#
D-RAS# D-WE#
D-VSSQ D-VCCQ
C1
D-A10
C2
AVD#
C3
VSS
C4
CLK
C5
RFU
C6
RFU
C7
RFU
C8
RFU
C9
RFU
C10
RFU
D1
D-A0
D2
F-WP#
D3
A7
D4
D-DM0
D5
F-ACC
D6
WE#
D7
A8
D8
A11
D9
F2-CE#
D10
D-A5
Legend
E1
D-VCCQ
E2
A3
E3
A6
E4
D-DM1
E5
F-RST#
E6
RFU
E7
A19
E8
A12
E9
A15
E10
D-VCCQ
Flash 1 only
F1
D-VSSQ
F2
A2
F3
A5
F4
A18
F5
F-RDY
F6
A20
F7
A9
F8
A13
F9
A21
F10
D-VSSQ
SDRAM only
G1
D-DQ0
G2
A1
G3
A4
G4
A17
G6
A23
G7
A10
G8
A14
G9
A22
G10
D-DQ15
H1
D-DQ1
H2
A0
H3
VSS
H4
DQ1
H7
DQ6
H8
RFU
H9
A16
H10
D-DQ14
Reserved for Future Use
J1
J2
J3
OE#
J4
DQ9
J5
DQ3
J6
DQ4
J7
DQ13
J8
DQ15
J9
RFU
J10
D-DQ13
Flash 2 only
D-DQ2 F1-CE#
K1
D-DQ3
K2
RFU
K3
DQ0
K4
DQ10
K5
F-VCC
K6
RFU
K7
DQ12
K8
DQ7
K9
VSS
K10
D-DQ12
Flash Shared
L1
D-DQ4
L2
RFU
L3
DQ8
L4
DQ2
L5
DQ11
L6
RFU
L7
DQ5
L8
DQ14
L9
RFU
L10
D-DQ11
M1
D-DQ5
M2
RFU
M3
RFU
M4
VSS
M5
F-VCC
M6
RFU
M7
RFU
M8
RFU
M9
RFU
M10
D-DQ10
N1
RFU
N2
D-BA0
N3
D-DQ6
N4
D-DQ7
N5
N6
N7
D-DQ8
N8
D-DQ9
N9
D-BA1
N10
RFU
D-VSSQ D-VCCQ
P1
RFU
P2
D-VSS
P3
D-A1
P4
D-A2
P5
D-VSS
P6
D-VCC
P7
D-A3
P8
D-A4
P9
RFU
P10
RFU
Note: M8 is RFU for SDR-DRAM and F-VCCQ for DDR-DRAM, as indicated in subsequent connection diagrams.
6
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
Advance
Information
3.2
2 x 256Mb NOR Flash with 128Mb SDRAM
137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1
D-CKE
A2 D-CLK
A3
RFU
A4
RFU
A5
D-VSS
A6
D-VCC
A7
RFU
A8
D-A11
A9
D-VSS
A10
D-CE#
B1
B2
B3
D-A9
B4
D-A8
B5
B6
B7
D-A7
B8
D-A6
B9
RFU
B10
D-CAS#
D-RAS# D-WE#
D-VSSQ D-VCCQ
C1
D-A10
C2
AVD#
C3
VSS
C4
CLK
C5
RFU
C6
RFU
C7
RFU
C8
RFU
C9
RFU
C10
RFU
D1
D-A0
D2
F-WP#
D3
A7
D4
D-DM0
D5
F-ACC
D6
WE#
D7
A8
D8
A11
D9
F2-CE#
D10
D-A5
Legend
E1
D-VCCQ
E2
A3
E3
A6
E4
D-DM1
E5
F-RST#
E6
RFU
E7
A19
E8
A12
E9
A15
E10
D-VCCQ
Flash 1 only
F1
D-VSSQ
F2
A2
F3
A5
F4
A18
F5
F-RDY
F6
A20
F7
A9
F8
A13
F9
A21
F10
D-VSSQ
SDRAM only
G1
D-DQ0
G2
A1
G3
A4
G4
A17
G6
A23
G7
A10
G8
A14
G9
A22
G10
D-DQ15
Reserved for Future Use
H1
D-DQ1
H2
A0
H3
VSS
H4
DQ1
H7
DQ6
H8
RFU
H9
A16
H10
D-DQ14
Flash 2 only
J1
J2
J3
OE#
J4
DQ9
J5
DQ3
J6
DQ4
J7
DQ13
J8
DQ15
J9
RFU
J10
D-DQ13
D-DQ2 F1-CE#
K1
D-DQ3
K2
RFU
K3
DQ0
K4
DQ10
K5
F-VCC
K6
RFU
K7
DQ12
K8
DQ7
K9
VSS
K10
D-DQ12
Flash Shared
L1
D-DQ4
L2
RFU
L3
DQ8
L4
DQ2
L5
DQ11
L6
RFU
L7
DQ5
L8
DQ14
L9
RFU
L10
D-DQ11
M1
D-DQ5
M2
RFU
M3
RFU
M4
VSS
M5
F-VCC
M6
RFU
M7
RFU
M8
RFU
M9
RFU
M10
D-DQ10
N1
RFU
N2
D-BA0
N3
D-DQ6
N4
D-DQ7
N5
N6
N7
D-DQ8
N8
D-DQ9
N9
D-BA1
N10
RFU
D-VSSQ D-VCCQ
P1
RFU
P2
D-VSS
P3
D-A1
P4
D-A2
P5
D-VSS
P6
D-VCC
P7
D-A3
P8
D-A4
P9
RFU
P10
RFU
Note: M8 is RFU for SDR-DRAM and F-VCCQ for DDR-DRAM, as indicated in subsequent connection diagrams.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
7
Advance
Information
3.3
256Mb NOR Flash with 128Mb SDR/DDR-DRAM
137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1
D-CKE
A2 D-CLK
A3
D-CLK#
A4
RFU
A5
D-VSS
A6
D-VCC
A7
RFU
A8
D-A11
A9
D-VSS
A10
D-CE#
B1
B2
B3
D-A9
B4
D-A8
B5
D-VSSQ
B6
D-VCCQ
B7
D-A7
B8
D-A6
B9
RFU
B10
D-CAS#
D-RAS# D-WE#
C1
D-A10
C2
AVD#
C3
VSS
C4
CLK
C5
RFU
C6
RFU
C7
RFU
C8
RFU
C9
RFU
C10
RFU
D1
D-A0
D2
F-WP#
D3
A7
D4
D-DM0
D5
F-ACC
D6
WE#
D7
A8
D8
A11
D9
RFU
D10
D-A5
Legend
E1
D-VCCQ
E2
A3
E3
A6
E4
D-DM1
E5
F-RST#
E6
RFU
E7
A19
E8
A12
E9
A15
E10
D-VCCQ
Flash 1 only
F1
D-VSSQ
F2
A2
F3
A5
F4
A18
F5
F-RDY
F6
A20
F7
A9
F8
A13
F9
A21
F10
D-VSSQ
SDRAM only
G1
D-DQ0
G2
A1
G3
A4
G4
A17
G6
A23
G7
A10
G8
A14
G9
A22
G10
D-DQ15
H1
D-DQ1
H2
A0
H3
VSS
H4
DQ1
H7
DQ6
H8
RFU
H9
A16
H10
D-DQ14
Reserved for Future Use
J1
J2
J3
OE#
J4
DQ9
J5
DQ3
J6
DQ4
J7
DQ13
J8
DQ15
J9
RFU
J10
D-DQ13
Flash 2 only
D-DQ2 F1-CE#
K1
D-DQ3
K2
RFU
K3
DQ0
K4
DQ10
K5
F-VCC
K6
RFU
K7
DQ12
K8
DQ7
K9
VSS
K10
D-DQ12
Flash Shared
L1
D-DQ4
L2
RFU
L3
DQ8
L4
DQ2
L5
DQ11
L6
RFU
L7
DQ5
L8
DQ14
L9
RFU
L10
D-DQ11
DDR only
M1
D-DQ5
M2
RFU
M3
RFU
M4
VSS
M5
F-VCC
M6
RFU
M7
RFU
M8
F-VCCQ
M9
RFU
M10
D-DQ10
N1
RFU
N2
D-BA0
N3
D-DQ6
N4
D-DQ7
N5
D-VSSQ
N6
D-VCCQ
N7
D-DQ8
N8
D-DQ9
N9
D-BA1
N10
RFU
P1
P2
P3
D-A1
P4
D-A2
P5
D-VSS
P6
D-VCC
P7
D-A3
P8
D-A4
P9
RFU
P10
D-DQS1
D-DQS0 D-VSS
Note: DDR-only signals are RFUs in the case of the SDR-DRAM based MCPs.
8
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
Advance
Information
3.4
512 Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256-Mb SDRAM on Bus 2
3.4.1 x16 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array (Top View, Balls
A1 D-CKE
A2 D-CLK
A3 RFU
A4 RFU
A5 D-VSS
A6 D-VCC
A7 D-A12
A8 D-A11
A9 D-VSS B9 RFU
A10 D-CE#
B1 D-RAS#
B2 D-WE#
B3 D-A9
B4 D-A8
B5 D-VSSQ C5 F2-CE#
B6 D-VCCQ C6 F-VCC D6 WE#
B7 D-A7
B8 D-A6
B10 D-CAS#
Legend
C1 D-A10
C2 AVD#
C3 VSS D3 A7
C4 CLK
C7 N-PRE
C8 N-ALE
C9 N-CLE
C10 RFU Reserved for Future Use
D1 D-A0
D2 F-WP#
D4 D-DM0
D5 F-ACC
D7 A8
D8 A11
D9 N-CE#
D10 D-A5 Do Not Use
E1 D-VCCQ F1 D-VSSQ G1 D-DQ0
E2 A3
E3 A6
E4 D-DM1
E5 F-RST#
E6 DNU
E7 A19
E8 A12
E9 A15
E10 D-VCCQ F10 D-VSSQ G10 D-DQ15 NAND Flash 1 Only NOR Flash 2 Only NOR Flash 1 Only
F2 A2
F3 A5
F4 A18
F5 RDY
F6 A20
F7 A9
F8 A13
F9 A21
G2 A1
G3 A4
G4 A17
G6 A23
G7 A10
G8 A14
G9 A22
H1 D-DQ1
H2 A0
H3 VSS
H4 DQ1
H7 DQ6
H8 RFU
H9 A16
H10 D-DQ14
J1 D-DQ2
J2 F1-CE#
J3 OE#
J4 DQ9
J5 DQ3
J6 DQ4
J7 DQ13
J8 DQ15
J9 DNU
J10 D-DQ13
DRAM Only
K1 D-DQ3 L1 D-DQ4
K2 DNU L2 N-VCC
K3 DQ0 L3 DQ8
K4 DQ10 L4 DQ2
K5 F-VCC L5 DQ11
K6 N-VCC L6 RFU
K7 DQ12 L7 DQ5
K8 DQ7 L8 DQ14
K9 VSS L9 N-WP#
K10 D-DQ12 L10 D-DQ11 All Flash Shared NOR Flash Shared
M1 D-DQ5 N1 N-WE# P1 RFU
M2 RFU N2 D-BA0 P2 D-VSS
M3 RFU N3 D-DQ6 P3 D-A1
M4 VSS N4 D-DQ7 P4 D-A2
M5 F-VCC N5
M6 RFU N6
M7 DNU N7 D-DQ8 P7 D-A3
M8 F-VCCQ N8 D-DQ9 P8 D-A4
M9 RFU N9 D-BA1 P9 N-RY/BY#
M10 D-DQ10 N10 N-RE# P10 RFU
D-VSSQ D-VCCQ P5 D-VSS P6 D-VCC
Note: 1.DDR-only signals are RFU in the case of SDR-DRAM based MCPs.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
9
Advance
Information
3.5
512Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256 Mb SDRAM on Bus 2
3.5.1 x8 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1 D-CKE
A2 D-CLK
A3 RFU
A4 RFU
A5 D-VSS
A6 D-VCC
A7 D-A12
A8 D-A11
A9 D-VSS B9 RFU
A10 D-CE#
B1 D-RAS#
B2 D-WE#
B3 D-A9
B4 D-A8
B5 D-VSSQ C5 F2-CE#
B6 D-VCCQ C6 F-VCC D6 WE#
B7 D-A7
B8 D-A6
B10 D-CAS#
C1 D-A10
C2 AVD#
C3 VSS D3 A7
C4 CLK
C7 N-PRE
C8 N-ALE
C9 N-CLE
C10 RFU Legend
D1 D-A0
D2 F-WP#
D4 D-DM0
D5 F-ACC
D7 A8
D8 A11
D9 N-CE#
D10 D-A5
E1 D-VCCQ F1 D-VSSQ G1 D-DQ0
E2 A3
E3 A6
E4 D-DM1
E5 F-RST#
E6 DNU
E7 A19
E8 A12
E9 A15
E10 D-VCCQ F10 D-VSSQ G10 D-DQ15
Reserved for Future Use
F2 A2
F3 A5
F4 A18
F5 RDY
F6 A20
F7 A9
F8 A13
F9 A21
Do Not Use
G2 A1
G3 A4
G4 A17
G6 A23
G7 A10
G8 A14
G9 A22
NOR Flash 1 Only
H1 D-DQ1
H2 A0
H3 VSS J3 OE#
H4 DQ1
H7 DQ6
H8 RFU
H9 A16
H10 D-DQ14 NOR Flash 2 Only
J1 D-DQ2
J2 F1-CE#
J4 DQ9
J5 DQ3
J6 DQ4
J7 DQ13
J8 DQ15
J9 DNU
J10 D-DQ13 NAND Flash 1 Only
K1 D-DQ3 L1 D-DQ4
K2 DNU L2 N-VCC
K3 DQ0 L3 DQ8
K4 DQ10 L4 DQ2
K5 F-VCC L5 DQ11
K6 N-VCC L6 RFU
K7 DQ12 L7 DQ5
K8 DQ7 L8 DQ14
K9 VSS L9 N-WP#
K10 D-DQ12 L10 D-DQ11
DRAM Only
M1 D-DQ5 N1 N-WE# P1 RFU
M2 RFU N2 D-BA0 P2 D-VSS
M3 RFU N3 D-DQ6 P3 D-A1
M4 VSS N4 D-DQ7 P4 D-A2
M5 F-VCC N5
M6 RFU N6
M7 DNU N7 D-DQ8 P7 D-A3
M8 F-VCCQ N8 D-DQ9 P8 D-A4
M9 RFU N9 D-BA1 P9 DNU
M10 D-DQ10 N10 N-RE# P10 RFU
NOR Flash Shared
D-VSSQ D-VCCQ P5 D-VSS P6 D-VCC
All Flash Shared
10
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
Advance
Information
3.6
512Mb NOR Flash with 512-Mb NAND on Bus 1 and 512-Mb SDRAM on Bus 2
3.6.1 x16 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1 D-CKE
A2 D-CLK
A3 D-CLK#
A4 RFU
A5 D-VSS
A6 D-VCC
A7 D-A12
A8 D-A11
A9 D-VSS B9 RFU
A10 D-CE#
B1 D-RAS#
B2 D-WE#
B3 D-A9
B4 D-A8
B5 D-VSSQ C5 F2-CE#
B6 D-VCCQ C6 F-VCC D6 WE#
B7 D-A7
B8 D-A6
B10 D-CAS#
Legend
C1 D-A10
C2 AVD#
C3 VSS D3 A7
C4 CLK
C7 N-PRE
C8 N-ALE
C9 N-CLE
C10 RFU Reserved for Future Use
D1 D-A0
D2 F-WP#
D4 D-DM0
D5 F-ACC
D7 A8
D8 A11
D9 N-CE#
D10 D-A5 Do Not Use
E1 D-VCCQ F1 D-VSSQ G1 D-DQ0
E2 A3
E3 A6
E4 D-DM1
E5 F-RST#
E6 DNU
E7 A19
E8 A12
E9 A15
E10 D-VCCQ F10 D-VSSQ G10 D-DQ15 NAND Flash 1 Only NOR Flash 2 Only NOR Flash 1 Only
F2 A2
F3 A5
F4 A18
F5 RDY
F6 A20
F7 A9
F8 A13
F9 A21
G2 A1
G3 A4
G4 A17
G6 A23
G7 A10
G8 A14
G9 A22
H1 D-DQ1
H2 A0
H3 VSS
H4 DQ1
H7 DQ6
H8 RFU
H9 A16
H10 D-DQ14
J1 D-DQ2
J2 F1-CE#
J3 OE#
J4 DQ9
J5 DQ3
J6 DQ4
J7 DQ13
J8 DQ15
J9 DNU
J10 D-DQ13
DRAM Only
K1 D-DQ3 L1 D-DQ4
K2 DNU L2 N-VCC
K3 DQ0 L3 DQ8
K4 DQ10 L4 DQ2
K5 F-VCC L5 DQ11
K6 N-VCC L6 RFU
K7 DQ12 L7 DQ5
K8 DQ7 L8 DQ14
K9 VSS L9 N-WP#
K10 D-DQ12 L10 D-DQ11 All Flash Shared NOR Flash Shared
M1 D-DQ5 N1 N-WE# P1 D-DQS0
M2 RFU N2 D-BA0 P2 D-VSS
M3 RFU N3 D-DQ6 P3 D-A1
M4 VSS N4 D-DQ7 P4 D-A2
M5 F-VCC N5
M6 RFU N6
M7 DNU N7 D-DQ8 P7 D-A3
M8 F-VCCQ N8 D-DQ9 P8 D-A4
M9 RFU N9 D-BA1 P9
M10 D-DQ10 N10 N-RE# P10
DDR only
D-VSSQ D-VCCQ P5 D-VSS P6 D-VCC
N-RY/BY# D-DQS1
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
11
Advance
Information
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
3.6.2
Connection Diagram for 15 x 15 Package-on-Package
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A
NC
D-V SS
F-A1
F-V
SS
F-A3
F-A5
F-A7
F-A9
F-V
SSQ
N-CLE
F-A11
F-A13
F-A15
F-A17
F-V
SSQ
F-A19
F-A21
F-A23
RFU
RFU
N-V SS
NC
Legend
B
D-V SS
D-V DD
F-A0
F-V
CC
F-A2
F-A4
F-A6
F-A8
F-V
CCQ
N-ALE
F-A10
F-A12
F-A14
F-A16
F-V
CCQ
F-A18
F-A20
F-A22
RFU
N-V CC
F-V
CCQ
F-V
SSQ
No Connect C
N-WE#
N-RY/BY#
F-RST#
RFU
D
D-DQ1
D-DQ0
F1-CE#
F2-CE#
E
D-V SSQ
D-V DDQ
Reserved for Future Use
N1-CE#
RFU
F
D-DQ3
D-DQ2
N-RE# N-WP#
Control for NOR/PS/NAND G
D-DQ5 D-DQ4
F-WE#
F-WP#
H
D-V SSQ
D-V DDQ
D-WE# F-OE#
B: Data J
D-DQ7 D-DQ6
D-V DD D-V SS
K
D-DM0 D-DQS0
D-A0
D-A1
A: Addr L
D-DM1 D-DQS1
D-A2
D-A3
M
D-V SSQ
D-V DDQ
D-A4
D-A5
A: A/D. B: Data
N
D-DQ9
D-DQ8
D-A6
D-A7
P
D-V SS
D-V DD
D-BA0 D-BA1
B: Addr
R
D-DQ11
D-DQ10
D1-CS#
RFU
T
D-DQ13
D-DQ12
D-RAS# D-CAS#
Ground
U
D-V D-V SSQ DDQ
D-A8
D-A9
V
D-DQ15
D-DQ14
D-A10
D-A11
Power
W
D-CKE
D-CLK
D-A12
RFU
Y
RFU
D-CLK#
/ PP N-ACC
F-V
D-V
SS
Control for DDR, PS
AA
RFU
F-V
SS
F-V
CC
F-DQ0/ N-ADQ0
F-V
CCQ
F-DQ2/ N-ADQ2
F-DQ4/ N-ADQ4
F-V
CCQ
F-DQ6/ N-ADQ6
RFU
F-CLK
N-V CC
RFU
F-DQ8/ N-ADQ8
F-V
CCQ
F-DQ10/ N-ADQ10
F-DQ12/ N-ADQ12
F-V
CCQ
F-DQ14/ N-ADQ14
F-ADV#
D-V
DD
RFU
AB
NC
D-V DD
F-V
SSQ
F-DQ1/ N-ADQ1
F-V
SSQ
F-DQ3/ N-ADQ3
F-DQ5/ N-ADQ5
F-V
SSQ
F-DQ7/ N-ADQ7
RFU
RFU
N-V SS
RFU
F-DQ9/ N-ADQ9
F-V
SSQ
F-DQ11/ N-ADQ11
F-DQ13/ N-ADQ13
F-V
SSQ
F-DQ15/ N-ADQ15
F-WAIT
F-V
CCQ
NC
12
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
Advance
Information
3.7
Lookahead Diagram on Split Bus
A1 D-CKE
A2 D-CLK
A3 D-CLK#
A4 D-A14
A5 D-VSS
A6 D-VCC
A7 D-A12
A8 D-A11
A9 D-VSS
A10 D-CE#
B1 D-RAS#
B2 D-WE#
B3 D-A9
B4 D-A8
B5 D-VSSQ C5 F2-CE#
B6 D-VCCQ C6 F-VCC D6 F-WE#
B7 D-A7
B8 D-A6
B9 D-A13
B10 D-CAS#
C1 D-A10
C2 F-AVD#
C3 VSS D3 A7
C4 F-CLK
C7 N-PRE
C8 N-ALE
C9 N-CLE
C10 D-A15 Legend
D1 D-A0
D2 F-WP#
D4 D-DM0
D5 F-ACC
D7 A8
D8 A11
D9 N1-CE#
D10 D-A5
E1 D-VCCQ F1 D-VSSQ G1 D-DQ0
E2 A3
E3 A6
E4 D-DM1
E5 F-RST#
E6 DNU
E7 A19
E8 A12
E9 A15
E10 D-VCCQ F10 D-VSSQ G10 D-DQ15
x16 DRAM
F2 A2
F3 A5
F4 A18
F5 F-RDY
F6 A20
F7 A9
F8 A13
F9 A21
NOR Flash
G2 A1
G3 A4
G4 A17
G6 A23
G7 A10
G8 A14
G9 A22
NAND Flash
H1 D-DQ1
H2 A0
H3 VSS J3 F-OE#
H4 DQ1
H7 DQ6
H8 A24
H9 A16
H10 D-DQ14
Flash Shared
J1 D-DQ2
J2 F1-CE#
J4 DQ9
J5 DQ3
J6 DQ4
J7 DQ13
J8 DQ15
J9 DNU
J10 D-DQ13 Do Not Use
K1 D-DQ3 L1 D-DQ4
K2 DNU L2 N-VCC M2 A27 N2 D-BA0 P2 D-VSS
K3 DQ0 L3 DQ8
K4 DQ10 L4 DQ2
K5 F-VCC L5 DQ11
K6 N-VCC L6 A25
K7 DQ12 L7 DQ5
K8 DQ7 L8 DQ14
K9 VSS L9 N-WP#
K10 D-DQ12 L10 D-DQ11 DDR Only
M1 D-DQ5 N1 N-WE# P1 D-DQS0
M3 A26 N3 D-DQ6 P3 D-A1
M4 VSS N4 D-DQ7 P4 D-A2
M5 F-VCC N5
M6 N2-CE# N6
M7 DNU N7 D-DQ8 P7 D-A3
M8 F-VCCQ N8 D-DQ9 P8 D-A4
M9 D-CLK# N9 D-BA1 P9
M10 D-DQ10 N10 N-RE# P10
D-VSSQ D-VCCQ P5 D-VSS P6 D-VCC
N-RY/BY# D-DQS1
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
13
Advance
Information
3.8
NOR Flash and DRAM Input/Output Descriptions
A23-A0 DQ15-DQ0 F2-CE# F1-CE# OE# F-WE# F-VCC F-VCCq VSS RFU RDY CLK = = = = = = = = = = = = NOR Flash Address inputs Flash Data input/output, shared between NOR and ORNAND Flash. DQ0-DQ7 shared for x8 ORNAND NOR Flash Chip-enable input # 2. Asynchronous relative to CLK for burst mode. NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode. NOR Flash Output Enable input. Asynchronous relative to CLK for Burst mode. NOR Flash Write Enable input. NOR Flash device power supply (1.7 V - 1.95V). Input/Output Buffer power supply. Ground Reserved for Future Use Flash ready output. Indicates the status of the Burst read. VOL = data valid. Shared between NOR and ORNAND Flash. NOR Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. NOR Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs NOR Flash hardware reset input. VIL= device resets and returns to reading array data NOR Flash hardware write protect input. VIL = disables program and erase functions in the four outermost sectors. NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. SDRAM Address inputs SDRAM Data input/output SDRAM System Clock SDRAM Chip Select SDRAM Clock Enable SDRAM Bank Select SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Data Input/Output Mask SDRAM Write Enable input SDRAM Ground SDRAM Input/Output Buffer ground SDRAM Input/Output Buffer power supply SDRAM device power supply
AVD#
=
F-RST# F-WP# F-ACC
= = =
D-A12-D-A0 D-DQ15-D-DQ0 D-CLK D-CE# D-CKE D-BA1-BA0 D-RAS# D-CAS# D-DM1-D-DM0 D-WE# D-VSS D-VSSQ D-VCCQ D-VCC
= = = = = = = = = = = = = =
14
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
Advance
Information
3.8.1
ORNAND Signal Descriptions
N-PRE N-ALE N-CLE N-CE# N-WP# N-WE# N-RE# N-RY/BY# N-I/O0-N-I/O15 N-VCC = = = = = = = = = = ORNAND Power-On Read Enable. Tie to VSS on customer board if not used ORNAND Address Latch Enable ORNAND Command Latch Enable ORNAND Chip-enablE ORNAND Write-protect ORNAND Write-enable ORNAND Read-enable ORNAND Ready-Busy--this is shared with NOR RDY ORNAND I/O Signals (I/O0-I/O7 for x8 bus width) ORNAND Power Supply
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
15
Advance
Information
4
Ordering Information
The order number is formed by a valid combinations of the following: 512 N EG BA W 4 Y 0
PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel MODEL NUMBER Refer to the Valid Combinations Tables PACKAGE MODIFIER Refer to the Valid Combinations Tables TEMPERATURE RANGE W = Wireless (-25C to +85C) PACKAGE TYPE BA = Very-thin Fine-pitch BGA Lead (Pb)-free compliant package BF = Very-thin Fine-pitch BGA Lead (Pb)-free package KF = Fine-pitch Package-on-Package (PoP) Lead (Pb)-free SDRAM EE = DE = D0 = FG = EG = EF = FF = & DATA FLASH DENSITY 256 Mb SDRAM, 256 Mb Data Flash 128 Mb SDRAM, 256 Mb Data Flash 128 Mb SDRAM, No Data Flash 512 Mb SDRAM, 1024 Mb ORNAND Flash 256 Mb SDRAM, 1024 Mb ORNAND Flash 256Mb SDRAM, 512Mb NAND Flash 512Mb SDRAM, 512Mb NAND Flash
S72WS
PROCESS TECHNOLOGY N = 110 nm, MirrorBitTM Technology CODE FLASH DENSITY 256 = 256Mb 512 = 512Mb PRODUCT FAMILY S72WS Multi-chip Product (MCP) 1.8-volt Simultaneous Read/Write, Burst Mode Flash Memory and Mobile SDRAM on Split Bus
16
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
Advance
Information
S72WS256ND0 Valid Combinations Base Ordering Part Number Package & Temperature BFW S72WS256ND0 BAW, BFW KFW Model Number 93 B7 BB D3 0, 2, 3 (Note 1) Packing Type
NOR Flash Burst Speed 66 MHz 54 MHz
SDRAM Supplier Supplier 5 Supplier 1 Supplier 2
SDRAM Burst Speed 133 MHz 104 MHz 133 MHz
Package Type
Package Marking
9x12x1.2mm 137-ball (Note 2)l 15x15x1.25mm 160-ball
66 MHz
Supplier 5
S72WS256NDE Valid Combinations Base Ordering Part Number S72WS256NDE Package & Temperature BAW, BFW Model Number U7 UB Packing Type 0, 2, 3 (Note 1)
NOR Flash Burst Speed 54 MHz
SDRAM Supplier Supplier 1 Supplier 2
SDRAM Burst Speed 104 MHz
Package Type 9x12x1.4mm 137-ball
Package Marking (Note 2)
S72WS256NEE Valid Combinations Base Ordering Part Number S72WS256NEE Package & Temperature BAW, BFW Model Number U7 UB Packing Type 0, 2, 3 (Note 1)
Flash Burst Speed 54 MHz
SDRAM Supplier Supplier 1 Supplier 2
SDRAM Burst Speed 104 MHz
Package Type 9x12x1.4mm 137-ball
Package Marking (Note 2)
S72WS512NFF Valid Combinations Base Ordering Part Number Package & Temperature BAW, BFW ZJ KFW BAW, BFW S72WS512NFF KFW BAW, BFW ZT KFW Z2 Model Number Packing Type
Flash Speed
DRAM Supplier
DRAM Speed
Package 11 x 13 mm 137-ball 15 x 15 5mm 160-ball 11 x 13 mm 137-ball 15 x 15 5mm 160-ball 11 x 13 mm 137-ball 15 x 15 5mm 160-ball
Package Marking
DRAM Type 1
0, 2, 3 (Note 1)
66 MHz
DRAM Type 5
133 MHz
(Note 2)
DRAM Type 2
June 1, 2006 S72WS-N_00_A8
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Information
S72WS512NFG Valid Combinations Base Ordering Part Number Package & Temperature Model Number L7 L6 L5 47 46 45 LZ LY LW 4Z 4Y S72WS512NFG BAW, BFW 4W N7 N6 N5 67 66 65 NZ NY NW 6Z 6Y 6W S72WS512NEG Valid Combinations Base Ordering Part Number Package & Temperature Model Number LZ LY LW 4Z 4Y S72WS512NEG BAW, BFW 4W NZ NY NW 6Z 6Y 6W 0, 2, 3 (Note 1) Packing Type 0, 2, 3 (Note 1) Packing Type
Flash Burst Speed
SDRAM Supplier
SDRAM Burst Speed
Package Type
Package Marking
DRAM Type 4
DRAM Type 2
54 MHz
104 MHz
11x13x1.4mm 137-ball
(Note 2)
DRAM Type 4
DRAM Type 2
Flash Burst Speed
SDRAM Supplier
SDRAM Burst Speed
Package Type
Package Marking
54 MHz
DRAM Type 2
104 MHz
11x13.1x1.4mm 137-ball
(Note 2)
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Information
S72WS512NEF Valid Combinations Base Ordering Part Number S72WS512NEF Package & Temperature KFW Model Number HJ Packing Type 0, 2, 3 (Note 1)
Flash Burst Speed 66 MHz
SDRAM Supplier
SDRAM Burst Speed 133 MHz
Package Type 15x15x1.2 mm 160-ball
Package Marking (Note 2)
DRAM Type 2
Notes: 1. Packing Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
June 1, 2006 S72WS-N_00_A8
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5
5.1
Physical Dimensions
TLD137--137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE 7 E1
E eE
3 2 1
INDEX MARK PIN A1 CORNER 10
P NML K J
HG F
EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
137X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TLD 137 N/A 12.00 mm x 9.00 mm PACKAGE MIN --0.17 0.81 NOM ------12.00 BSC. 9.00 BSC. 10.40 BSC. 7.20 BSC. 14 10 137 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. G5,H5,H6 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3393\ 16-038.22a
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Information
5.2
FEA137--137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package
D
0.15 (2X) C
10 9 8 7 6 5 4
A
D1 eD
SE
7
E eE
E1
3 2 1
INDEX MARK PIN A1 CORNER 9
P NML K J
HG F
EDC
BA
B
7
C
TOP VIEW
0.15 (2X)
SD
Pin A1 Corner
A A2 A1
6
0.20
C
BOTTOM VIEW
SIDE VIEW b
M CAB MC
C
0.08
C
137X
0.15 0.08
NOTES:
PACKAGE JEDEC DXE SYMBOL MIN.
0.10 1.11
FEA 137
N/A
12.00mm X 9.00mm PACKAGE
1.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010.
NOTE
MAX.
1.40 1.26 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT 0.45 BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT
2. 3.
NOM.
12.00 BSC 9.00 BSC 10.40 BSC 7.20 BSC
A A1 A2 D E D1 MD ME n
4. 5.
e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6 7
14 10 1.37 0.35 0.40 0.80 BSC 0.80 BSC 0.40 BSC G5, H5, H8
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2
b
eE eD SD/SE
8.
DEPOPULATED SOLDER BALLS
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
9.
June 1, 2006 S72WS-N_00_A8
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5.3
FVD137--137-ball Fine-Pitch Ball Grid Array (FBGA) 11 x 13 mm Package
D
0.15 C (2X)
10 9 8 7 6 5 4 3 2 1
A
eD
D1
SE
7
E eE
E1
P
NM
LK
J
HGF
E
DCB
A
PIN A1 CORNER
9 INDEX MARK
B
7
PIN A1 CORNER
TOP VIEW A A2 A1
6
0.15 C (2X) 0.20 C
SD
BOTTOM VIEW
SIDE VIEW b
C
0.08 C
137X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD SE 0.35 FVD 137 N/A 13.00 mm x 11.00 mm PACKAGE MIN --0.10 1.09 NOM ------13.00 BSC. 11.00 BSC. 10.40 BSC. 7.20 BSC. 14 10 137 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. G5,H5,H6 0.45 MAX 1.40 --1.24 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 6 7 4. 5. NOTE 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3522 \ 16-038.21 \ 09.29.05
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S72WS-N Based MCP/PoP Products
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Information
5.4
BWA160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD
A B C D E F G H J K L M N P R T U V W Y AA AB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
SE 7 E1
E eE
0.10 C (2X)
B
SD
7
TOP VIEW
0.10 C (2X)
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.10 C
SIDE VIEW b
M C AB MC
NOTES: 1. 2. NOTE 3. 4. PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PARAMETERS 0.50 BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 7 6 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
160X
0.15 0.08
PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SD SE 0.40
BWA 160 N/A 15.00 mm x 15.00 mm PACKAGE MIN --0.35 0.74 NOM ------15.00 BSC. 15.00 BSC. 13.65 BSC. 13.65 BSC. 22 22 160 160 2 0.45 0.65 BSC. 0.65 BSC. 0.325 BSC. C3~C20,D3~D20,E3~E20,F3~F20 G3~G20,H3~H20,J3~J20,K3~K20 L3~L20,M3~M20,N3~N20,P3~P20 R3~R20,T3~T20,U3~U20,V3~V20 W3~W20,Y3~Y20 MAX 1.25 --0.84
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3518 \ 16-038.46 \ 02.23.06
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Information
5.5
BWB160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD
A B C D E F G H J K L M N P R T U V W Y AA AB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
SE 7 E1
E eE
0.10 C (2X)
B
SD
7
TOP VIEW
0.10 C (2X)
BOTTOM VIEW
A
A2 A1
6
0.20 C
C
0.10 C
SIDE VIEW b
M C AB MC
160X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SD / SE 0.45 BWB 160 N/A 15.00 mm x 15.00 mm PACKAGE MIN --0.40 0.74 NOM ------15.00 BSC. 15.00 BSC. 13.65 BSC. 13.65 BSC. 22 22 160 160 2 0.50 0.65 BSC. 0.65 BSC. 0.325 BSC. C3~C20,D3~D20,E3~E20,F3~F20 G3~G20,H3~H20,J3~J20,K3~K20 L3~L20,M3~M20,N3~N20,P3~P20 R3~R20,T3~T20,U3~U20,V3~V20 W3~W20,Y3~Y20 0.55 MAX 1.30 --0.84 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PARAMETERS BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 7 6 NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3523 \ 16-038.46 \ 02.23.06
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Information
5.6
BTA160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD
A B C D E F G H J K L M N P R T U V W Y AA AB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
SE 7 E1
E eE
0.10 C (2X)
B
SD
7
TOP VIEW A A2 A1
6
0.10 C (2X) 0.20 C
BOTTOM VIEW
C
0.10 C
SIDE VIEW b
C AB C
160X
0.15 M 0.08 M
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SD SE 0.45 BTA 160 N/A 15.00 mm x 15.00 mm PACKAGE MIN --0.40 0.74 NOM ------15.00 BSC. 15.00 BSC. 13.65 BSC. 13.65 BSC. 22 22 160 160 2 0.50 0.65 BSC. 0.65 BSC. 0.325 BSC. C3~C20,D3~D20,E3~E20,F3~F20 G3~G20,H3~H20,J3~J20,K3~K20 L3~L20,M3~M20,N3~N20,P3~P20 R3~R20,T3~T20,U3~U20,V3~V20 W3~W20,Y3~Y20 0.55 MAX 1.30 --0.84 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PARAMETERS BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 7 6 NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3550 \ 16-038.55 \ 02.23.06
June 1, 2006 S72WS-N_00_A8
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Information
5.7
ALH160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD
A B C D E F G H J K L M N P R T U V W Y AA AB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
SE 7 E1
E eE
0.10 C (2X)
B
SD
7
TOP VIEW
0.10 C (2X)
BOTTOM VIEW
0.10 C
A A2 A1
6
C
0.10 C
SIDE VIEW b
160X
0.15 M C A B 0.08 M C
PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SE SD 0.45
ALH 160 N/A 15.00 mm x 15.00 mm PACKAGE MIN --0.40 0.53 NOM ------15.00 BSC. 15.00 BSC. 13.65 BSC. 13.65 BSC. 22 22 160 160 2 0.50 0.65 BSC. 0.65 BSC 0.325 BSC. C3-C20,D3-D20,E3-E20, F3-F20,G3-G20,H3-H20, J3-J20,K3-K20,L3-L20, M3-M20,N3-N20,P3-P20, R3-R20,T3-T20,U3-U20, V3-V20,W3-W20,Y3-Y20 0.55 MAX 1.10 --0.65 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PERIMETERS BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS NOTE
NOTES: 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 7 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. 9 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3553 \ 16-038.24 \ 3.21.06
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Information
6
MCP Revision Summary
Revision A (August 26, 2004)
Initial release
Revision A 1 (June 1, 2005)
Added SDRAM Type 2 module Added Lead (Pb)-free options Added FEA137 package diagram
Revision A2 (October 7, 2005)
Global Updated the S29WS-N NOR Flash Module Added the S30MS-P ORNAND Flash Module Added SDRAM Type 4 module Product Selector Guide Updated the Product Selector Guide Connection Diagrams Added two diagrams for the x8 and x16 ORNAND connections Pin Descriptions Updated descriptions and added descriptions for ORNAND signals Ordering Information Added new options Added Package-on-Package (PoP) options Valid Combinations Updated the valid combinations tables Physical Dimensions Added the FGA137 package diagram Added the BWA160 package diagram Added the BWB160 package diagram
Revision A3 (November 9, 2005)
Updated the SDRAM Type 1 module Changed the status of all RAM modules to Preliminary from Advanced.
Revision A4 (December 14, 2005)
Product Selector Guides Updated the tables Connection Diagrams Added the 512 Mb NOR Flash with 512 Mb NAND on Bus 1 and 512 Mb SDRAM on Bus 2 diagram Ordering Information Added new model number, package modifier and SDRAM & Data Flash density options
June 1, 2006 S72WS-N_00_A8
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Advance
Information
Valid Combinations Updated all tables with new options
Revision A5 (December 16, 2005)
Connection Diagrams Updated the pinouts to include DDR signals Qualified 133 MHz as DDR based frequency
Revision A6 (March 21, 2006)
NOR Flash + ORNAND Flash + DRAM MCPs Product Selector Guide Updated the model numbers Ordering Information Table Updated the table Valid Combinations Updated the tables Physical Dimensions Added the ALH160 package
Revision A7 (April 18, 2006)
Connection Diagrams Updated the pinouts
Revision A8 (June 1, 2006)
Added 2 OPNs for products with DRAM Type 5 Updated product selector guide Updated valid combination table Added BTA160 package diagram
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c)2004-2006 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.
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S72WS-N Based MCP/PoP Products
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